MC14043BDG, Защелка, MC14043, SR, С Тремя Состояниями, 175 нс, 8.8 мА, SOIC
- Производитель
- ON Semiconductor
- Полное описание
The MC14043BDG is a quad R-S Latch constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. Each latch has an independent Q output and set and reset inputs. The Q outputs are gated through three-state buffers having a common enable input. The outputs are enabled with a logical 1 or high on the enable input, a logical 0 or low disconnects the latch from the Q outputs, resulting in an open circuit at the Q outputs. The outputs are capable of driving two low-power TTL loads or one low-power Schottky TTL load over the rated temperature range. This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
• Double diode input protection
• Three-state outputs with common enable
Полупроводники - Микросхемы\Логика\Триггеры-защелки
Технические параметры
| Выходной Ток | 8.8мА |
| Минимальная Рабочая Температура | -55 C |
| Максимальная Рабочая Температура | 125 C |
| Максимальное Напряжение Питания | 18В |
| Минимальное Напряжение Питания | 3В |
| Количество Выводов | 16вывод(-ов) |
| Тип Выхода Микросхемы | С Тремя Состояниями |
| Количество Бит | 4бит |
| Задержка Распространения | 175нс |
| Стиль Корпуса Микросхемы Логики | SOIC |
| Тип Защелки | sr |
| Базовый Номер / Семейство Логики | MC14043 |
| Базовый Номер Микросхемы Логики | 4043 |
| Семейство Логической Микросхемы | MC140 |
| EU RoHS | Compliant |
| ECCN (US) | EAR99 |
| Part Status | Active |
| HTS | 8542.39.00.01 |
| Type | SR-Type |
| Logic Family | 4000 |
| Latch Mode | Transparent |
| Number of Channels per Chip | 4 |
| Number of Elements per Chip | 1 |
| Number of Inputs per Chip | 8 |
| Number of Input Enables per Element | 0 |
| Number of Selection Inputs per Element | 0 |
| Number of Outputs per Chip | 4 |
| Number of Output Enables per Element | 1 |
| Bus Hold | No |
| Set/Reset | No |
| Polarity | Non-Inverting |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 175@10V|120@15V|350@5V |
| Absolute Propagation Delay Time (ns) | 350 |
| Process Technology | CMOS |
| Output Type | 3-State |
| Maximum Low Level Output Current (mA) | 4.2(Min) |
| Maximum High Level Output Current (mA) | -4.2(Min) |
| Minimum Operating Supply Voltage (V) | 3 |
| Typical Operating Supply Voltage (V) | 12|15|5|3.3|9 |
| Maximum Operating Supply Voltage (V) | 18 |
| Typical Quiescent Current (uA) | 0.006 |
| Maximum Quiescent Current (uA) | 4 |
| Propagation Delay Test Condition (pF) | 50 |
| Minimum Operating Temperature (C) | -55 |
| Maximum Operating Temperature (C) | 125 |
| Supplier Temperature Grade | Automotive |
| Packaging | Tube |
| Pin Count | 16 |
| Supplier Package | SOIC |
| Standard Package Name | SOP |
| Mounting | Surface Mount |
| Package Height | 1.5(Max) |
| Package Length | 10(Max) |
| Package Width | 4(Max) |
| PCB changed | 16 |
| Lead Shape | Gull-wing |
| Вес, г | 0.314 |